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14-bit, 80 msps, a/d converter ad9444 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures 80 msps guar a n teed samplin g rate 100 db two-to ne sfdr with 6 9 .3 mhz and 70 .3 mhz 73.1 db s n r wi th 70 mh z inpu t 97 dbc sfdr wi th 70 mh z inpu t excellent linea r ity dn l = 0.4 lsb ty pical in l = 0.6 lsb ty pical 1.2 w power di ssipation 3.3 v and 5 v s u pply o p eratio n 2.0 v p-p differ e ntial f u ll-sca l e input lvds outputs ( a nsi-64 4 compatible) data format s e l e ct output clock available applic a t io ns multicarrier, m u ltimode cellular receivers antenna array positioning power amplifie r linearization b r o a dband wireless radar, infar e d i m aging communications instrumenta t ion gener a l description the ad9444 is a 14-b i t m o n o li t h ic, s a m p lin g analog-t o-dig i tal co n v er t e r (ad c ) wi t h an o n -chi p , t r ack - an d - hold cir c ui t an d i s o p t i mi ze d fo r p o w e r , sma l l size, a nd e a s e o f us e. the p r o d uc t o p era t es a t u p to a n 80 ms ps c o n v ersio n r a t e and is o p timized fo r m u l t ica r r i er , m u l t i m o d e r e c e i v ers, s u ch as t h os e fo und i n ce l l u l a r inf r as tr uc t u r e eq ui p m en t. the ad c r e q u ir es 3.3 v a nd 5. 0 v p o w e r s u p p lies a nd a lo w v o l t a g e dif f er en t i al i n p u t clo c k fo r f u l l p e rfo r m a n c e o p era t io n. n o ext e r n al r e fer e n c e o r dr i v er co m p on e n ts a r e r e q u ir e d fo r m a n y ap p l i c at i o n s . d a t a o u t p u t s a r e l v d s - c o m p a t i b l e ( a n s i - 644) o r cm os-co m p a t i b l e an d in c l ude t h e m e an s t o r e d u ce t h e o v eral l c u r r en t n e e d e d fo r sh o r t t r ace di s t an ces. func ti on a l bl ock di a g r a m cmos or lvds output staging clock and timing management agnd drgnd drvdd vref clk+ vin+ ad9444 vin ? clk? dco 05089-001 avdd1 avdd2 dcs mode dfs output mode t/h buffer 14 pipeline adc 2 28 2 or d13?d0 ref refb sense reft fi g u r e 1 . o p t i o n al fe a t ur es al lo w us ers t o im ple m en t var i o u s s e le c t a b le op e r a t i n g c o nd it i o ns , i n clu d i n g d a t a for m a t s e l e c t an d output da ta m o d e . the ad9444 is a v a i la b l e in a 10 0-lead s u r f ace-m o u n t p l as tic p a c k a g e (100-le ad t q fp/ep) sp ecif ied o v er the ind u s t r i al t e m p era t ur e ra ng e (?40c t o +85c). produc t highlight s 1. h i g h p e r f o r ma n c e: o u t s t a nding s f dr p e r f o r ma nce fo r m u l - t i ca r r ier , m u l t im o d e 3g and 4 g ce l l u l a r b a s e st a t ion re c e ive r s . 2. e a s e of u s e : o n - c h i p re f e re nc e an d t r a c k - a n d - ho l d . a n o u t p u t c l o c k sim p lif i es da t a c a p t ur e . 3. p a c k a g e d in a p b -f r e e , 100-lead t q fp/ep . 4. c l o c k d c s m a i n t a i n s ove r a l l a d c p e r f or m a nc e ove r a w i d e ra n g e o f clo c k pu ls e wi d t h s . 5. or (o u t -o f-r a nge) o u t p uts i n di ca te w h e n t h e si g n a l is b e yo nd th e s e lect e d in p u t ra n g e .
ad9444* product page quick links last content update: 02/23/2017 comparable parts view a parametric search of comparable parts. documentation application notes ? an-1142: techniques for high speed adc pcb layout ? an-282: fundamentals of sampled data systems ? an-345: grounding for low-and-high-frequency circuits ? an-501: aperture uncertainty and adc system performance ? an-586: lvds outputs for high speed a/d converters ? an-715: a first approach to ibis models: what they are and how they are generated ? an-737: how adisimadc models an adc ? an-741: little known characteristics of phase noise ? an-756: sampled systems and the effects of clock phase noise and jitter ? an-807: multicarrier wcdma feasibility ? an-808: multicarrier cdma2000 feasibility ? an-835: understanding high speed adc testing and evaluation ? an-905: visual analog converter evaluation tool version 1.0 user manual ? an-935: designing an adc transformer-coupled front end data sheet ? ad9444: 14-bit, 80 msps, a/d converter data sheet tools and simulations ? visual analog ? ad9444 ibis models reference materials technical articles ? correlating high-speed adc performance to multicarrier 3g requirements ? ms-2210: designing power supplies for high speed adc design resources ? ad9444 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad9444 engineerzone discussions. sample and buy visit the product page to see pricing options. technical support submit a technical question or find your regional support number. document feedback submit feedback for this data sheet. this page is dynamically generated by analog devices, inc., and inserted into this data sheet. a dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. this dynamic page may be frequently modified.
ad9444 rev. 0 | page 2 of 40 table of contents dc specifications ............................................................................. 3 ac specifications .............................................................................. 4 digital specifications ........................................................................ 5 switching specifications .................................................................. 6 explanation of test levels ........................................................... 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 definitions of specifications ........................................................... 9 pin configurations and function descriptions ......................... 10 equivalent circuits ......................................................................... 14 typical performance characteristics ........................................... 15 theory of operation ...................................................................... 20 analog input and reference overview ................................... 20 clock input considerations ...................................................... 22 power considerations ................................................................ 23 digital outputs ........................................................................... 23 timing ......................................................................................... 23 operational mode selection ..................................................... 23 evaluation board ........................................................................ 24 lvds evaluation board schematics ........................................ 25 lvds mode evaluation board bill of materials (bom) ...... 30 cmos evaluation board schematics ...................................... 32 cmos mode evaluation board bill of materials (bom) ..... 37 outline dimensions ....................................................................... 39 ordering guide .......................................................................... 39 revision history 10/04revision 0: initial version
ad9444 rev. 0 | page 3 of 40 dc specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, lvds mode, sample rate = 80 msps, 2 v p-p differential input, internal trimmed reference (1.0 v mode), a in = ?0.5 dbfs, dcs on, unless otherwise noted. table 1. ad9444bsvz-80 parameter temp test level min typ max unit resolution full vi 14 bits accuracy no missing codes full vi guaranteed offset error full vi 6 0.3 6 mv gain error 1 full vi ?3.0 0.4 +3.0 % fsr differential nonlinearity (dnl) 2 full vi ?0.8 0.4 +0.8 lsb integral nonlinearity (inl) 2 25c i ?1.3 0.6 +1.3 lsb full vi ?1.7 +1.7 lsb temperature drift offset error full v 12 v/c gain error full v 0.002 %fs/c voltage reference output voltage 1 full vi 0.87 1.0 1.13 v load regulation @ 1.0 ma full v 2 mv reference input current (external 1.0 v reference) full vi 80 125 a input referred noise 25c v 1.0 lsb rms analog input input span full v 2 v p-p input common-mode voltage full v 3.5 v input resistance 3 full v 1 k? input capacitance 3 full v 2.5 pf power supplies supply voltage avdd1 full iv 3.14 3.3 3.46 v avdd2 full iv 4.75 5.0 5.25 v drvddlvds outputs full iv 3.0 3.6 v drvddcmos outputs full iv 3.0 3.3 3.6 v supply current avdd1 full vi 217 240 ma avdd2 2 full vi 71 80 ma idrvdd 2 lvds outputs full vi 55 62 ma idrvdd 2 cmos outputs full v 12 ma psrr offset full v 1 mv/v gain full v 0.2 %/v power consumption dc inputlvds outputs full vi 1.21 1.4 w dc inputcmos outputs full v 1.07 w sine wave input 2 lvds outputs full vi 1.25 w sine wave input 2 cmos outputs full v 1.11 w 1 the internal voltage reference is trimmed at fina l test to minimize the gain error of the ad9444. 2 measured at the maximum clock rate, f in = 15 mhz, full-scale sine wave, with a 100 ? differential termination on each pair of output bits for lvds output mode and approximately 5 pf loading on each output bit for cmos output mode. 3 input capacitance or resistance refers to the effective impedance between one differential input pin and agnd. refer to for the equivalent analog input structure. figure 6
ad9444 rev. 0 | page 4 of 40 ac specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, lvds mode, sample rate = 80 msps, 2 v p-p differential input, internal trimmed reference (1.0 v mode), a in = ?0.5 dbfs, dcs on, unless otherwise noted. table 2. ad9444bsvz-80 parameter temp test level min typ max unit signal-to-noise-ratio (snr) f in = 10 mhz 25c iv 73.0 74.0 db full iv 72.7 db f in = 35 mhz 25c i 72.4 73.7 db full iv 72.3 db f in = 70 mhz 25c iv 72.3 73.1 db full iv 72.0 db f in = 100 mhz 25c v 72.3 db signal-to-noise-and distortion (sinad) f in = 10 mhz 25c iv 73.0 74.0 db full iv 72.7 db f in = 35 mhz 25c i 72.4 73.7 db full iv 72.2 db f in = 70 mhz 25c iv 72.2 73.1 db full iv 72.0 db f in = 100 mhz 25c v 72.3 db effective number of bits (enob) f in = 10 mhz 25c v 12.1 bits f in = 35 mhz 25c v 12.0 bits f in = 70 mhz 25c v 11.9 bits f in = 100 mhz 25c v 11.8 bits spurious-free dynamic range (sfdr) f in = 10 mhz 25c iv 91 97 dbc full iv 87 dbc f in = 35 mhz 25c i 91 97 dbc full iv 87 dbc f in = 70 mhz 25c iv 90 97 dbc full iv 87 dbc f in = 100 mhz 25c v 96 dbc worst harmonic, second or third f in = 10 mhz 25c iv ?97 ?91 dbc full iv ?87 dbc f in = 35 mhz 25c i ?97 ?91 dbc full iv ?87 dbc f in = 70 mhz 25c iv ?97 ?90 dbc full iv ?87 dbc f in = 100 mhz 25c v ?96 dbc worst spur excluding second or harmonics f in = 10 mhz 25c iv ?102 ?93 dbc full iv ?93 dbc f in = 35 mhz 25c i ?103 ?93 dbc full iv ?93 dbc f in = 70 mhz 25c iv ?102 ?93 dbc full iv ?93 dbc f in = 100 mhz 25c v ?99 dbc two-tone sfdr f in = 10.8 mhz @ ?7 dbfs, 9.8 mhz @ ?7 dbfs 25c v ?102 dbfs f in = 70.3 mhz @ ?7 dbfs, 69.3 mhz @ ?7 dbfs 25c v ?100 dbfs analog bandwidth full v 650 mhz
ad9444 rev. 0 | page 5 of 40 digital specifications avdd1 = 3.3 v, avdd2 = 5.0 v, drvdd = 3.3 v, r lvdsbias = 3.74 k?, unless otherwise noted. table 3. ad9444bsvz-80 parameter temp test level min typ max unit cmos logic inputs (dfs, dcs mode, output mode) high level input voltage full iv 2.0 v low level input voltage full iv 0.8 v high level input current full vi +200 a low level input current full vi ?10 +10 a input capacitance full v 2 pf digital output bitscmos mode (d0 to d13, otr) 1 drvdd = 3.3 v high level output voltage full iv 3.25 v low level output voltage full iv 0.2 v digital output bits lvds mode (d0 to d13, otr) v od differential output voltage 2 full vi 247 545 mv v os output offset voltage full vi 1.125 1.375 v clock inputs (clk+, clk?) differential input voltage full iv 0.2 v common-mode voltage full vi 1.3 1.5 1.6 v differential input resistance full v 8 10 12 k? differential input capacitance full v 4 pf 1 output voltage levels measured with 5 pf load on each output. 2 lvds r term = 100 ?.
ad9444 rev. 0 | page 6 of 4 0 switching specifications a v d d 1 = 3.3 v , a v d d 2 = 5.0 v , d r vd d = 3.3 v , unles s o t h e r w is e n o t e d . table 4. ad94 44b svz - 8 0 p a r a m e t e r t e m p t e s t leve l m i n t y p m a x unit clo c k input p a rame ters maximum conv ersion rate full vi 80 msps minimum conversion rate full v 10 msps clk period full v 12.5 ns clk pulse width high 1 (t clk h ) f u l l v 4 n s clk pulse width low 1 (t clk l ) f u l l v 4 n s data outpu t param ete r s output propagation delaycmos (t pd ) 2 (dx, dc o+) full iv 3 5.25 8 ns output propagation delaylvds (t pd ) 3 (dx+, d c o+) full vi 3 5 7.5 ns pipeline del a y ( l atency) full v 12 cycles aperture delay ( t a ) f u l l v n s aperture uncertainty (j itter, t j ) f u l l v 0 . 2 p s r m s 1 wi t h dut y cyc l e st a b i l i z er (d c s ) en a b le d. 2 out p ut propa g a t i o n de la y i s m e a s ur e d from c l oc k 50% t r a n si t i on t o da t a 50% t r a n si t i on , wi t h 5 pf loa d . 3 lvds r term = 100 ? . measured from the 50% point of the r i sing edg e of clk+ to the 50% poi nt of the data transition. n? 12 n?11 n n+1 a in clk+ clk ? data out dco+ dco ? n n+1 n? 1 t clkh t clkl 1/ f s t pd 12 clock cycles t cpd 05089-002 f i gure 2. l v ds mod e tim i ng d i ag r a m
ad9444 rev. 0 | page 7 of 4 0 n+1 n+2 n? 1 t clkl 12 cycles 05089-003 n t clkh t pd vin clk+ clk ? dx dco+ dco? t dcopd n-12 n-11 n-1 n f i g u re 3. c m os ti ming d i ag r a m explanation of test levels test leve l definitions i 100% production tested. ii 100% production tested at 25c and samp le tested at specified temperatures. iii sample tested only. iv parameter is guaranteed by desi gn and charact e rization testing . v parameter is a typical va lue only. vi 100% production tested at 25c and gu aranteed by design and characterizati on for industrial temperature rang e.
ad9444 rev. 0 | page 8 of 4 0 absolute maximum ratings table 5. parameter with respect to m i n m a x u n i t electrical a v d d 1 a g n d ? 0 . 3 + 4 v a v d d 2 a g n d ? 0 . 3 + 6 v d r v d d d g n d ? 0 . 3 + 4 v a g n d d g n d ? 0 . 3 + 0 . 3 v a v d d 1 d r v d d ? 4 + 4 v a v d d 2 d r v d d ? 4 + 6 v a v d d 2 a v d d 1 ? 4 + 6 v d0 to d13 dgnd C0.3 drvdd + 0.3 v clk, mode agnd C0.3 avdd1 + 0.3 v vin+, vin? agnd C0.3 avdd2 + 0.3 v vref agnd C0.3 avdd1 + 0.3 v sense agnd C0.3 avdd1 + 0.3 v reft, refb agnd C0.3 avdd1 + 0.3 v environment a l storage temperature C65 +125 c operating tem p erature range C40 +85 c lead temperature range (sol dering 10 s e c) 3 0 0 c junction tempe r ature 150 c s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im plie d . e x p o sur e t o a b s o l u te max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . therma l resista n ce the h e a t sin k o f th e ad9444 p a c k a g e m u s t be s o lder ed t o g r ou nd. table 6. package type ja jb jc unit 100-lead tqfp/ep 19.8 8.3 2 c/w ty p i c a l ja = 19. 8c/w (h e a t-sink s o lder e d ) f o r m u l t il a y er boa r d in s t ill a i r . ty p i c a l jb = 8.3c/w (h e a t-sin k s o lder ed) f o r m u l t il a y er bo a r d in st i l l a i r . ty p i c a l jc = 2 c/w ( j u n c t ion to exp o s e d h e a t sink) r e p r es en ts th e t h e r m a l r e si s t a n ce th r o ugh h e a t - s ink p a th . a i r f low inc r e a s e s he a t di ss i p a t i o n e f fe c t ively re d u c i ng ja . a l s o , more me t a l d i re c t ly i n c o n t a c t w i t h t h e p a ck ag e l e a d s , f r om m e t a l t r a c e s , t h r o u g h h o l e s , g r o u n d , a n d p o w e r p l a n e s , r e d u c e s th e ja . i t is r e q u ir ed tha t the exp o s e d h e a t sin k b e s o lder ed t o th e gr o u n d p l a n e . esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprie - tary esd protect i on circuitry, permanent damag e may o ccur on devices subje c ted to high energy electrostatic discharges. ther efore, prop er esd precautions a r e reco mmende d to avoid performance degradation or lo ss of functionality.
ad9444 rev. 0 | page 9 of 4 0 definitions of specifications a n a l og bandw i d t h (f u l l p o w e r ba ndw i d t h) the a n alog in pu t f r e q uen c y a t w h ich t h e s p e c t r al p o w e r o f t h e f u ndam e n t a l f r e q uen c y (as de t e r m in e d b y t h e fft a n a l y s is) is re d u c e d by 3 d b . ap e r t u r e d e l a y ( t a ) the dela y b e tw e e n t h e 50% p o i n t o f t h e r i sin g e d g e o f t h e clo c k a nd t h e inst an t a t w h ich t h e a n a l og in p u t is s a m p le d . ap e r t u r e un c e r t a i n t y ( j i t t e r , t j ) the s a m p le-t o-s a m p le va r i a t ion in a p er t u r e dela y . c l o c k pu ls e w i d t h and d u ty cy cl e pulse w i d t h h i g h i s th e m i ni m u m a m o u n t o f tim e tha t t h e c l o c k p u ls e sh ou ld be lef t in t h e l o g i c 1 s t a t e to ac hie v e r a t e d p e r f o r ma n c e. pu ls e wi d t h lo w is t h e m i ni m u m t i me t h e clo c k p u ls e s h o u l d b e lef t in t h e lo w s t a t e . a t a g i v e n cl o c k ra te , t h es e sp e c if ic a t ion s d e f i n e an acc e p t ab le clo c k d u ty c y cle. d i f f erenti a l n o n l i n e a r i ty ( d n l , n o mi s s i n g c o d e s ) a n i d eal a d c exh i b i t s co d e tra n si ti o n s tha t a r e e x a c tl y 1 l s b a p a r t. dnl is t h e de v i a t io n f r o m t h is ide a l va lue . g u a r an t e e d n o mis s in g co des to 14-b i t r e s o l u tio n in dica t e s tha t al l 16384 co des m u s t b e p r es e n t o v er al l o p era t in g ra n g es. e f f e c t iv e n u mb er of b i ts (eno b) the ef fe c t i v e n u m b er o f b i ts fo r a sine w a v e i n pu t a t a g i v e n i n p u t f r eq ue n c y ca n be cal c ul a t ed d i r e ctl y f r o m i t s m e as ur ed s i n a d usin g t h e fol l o w in g fo rm u l a () 6.02 1.76 ? = sinad enob ga in er r o r the f i r s t co de tra n si tio n sh o u ld o c c u r a t an a n al og val u e ? ls b a b o v e n e ga t i v e f u l l s c ale . th e l a st t r a n si t i on sh ou ld o c c u r a t an a n alog val u e 1 ? ls b b e lo w t h e p o si t i v e f u l l s c ale . ga in er r o r is t h e de v i a t ion o f t h e ac t u al dif f er en ce b e tw e e n f i rs t an d las t co de t r a n si t i o n s a n d t h e id e a l dif f er e n ce b e tw e e n f i r s t an d last co de tra n s i ti o n s . in t e g r a l no n l i n e a r i t y ( i n l ) the d e v i a t ion of e a ch i n divi d u a l co de f r o m a li n e dr a w n f r o m n e ga ti v e full sc al e th r o u g h pos i t i v e full sc al e . th e po i n t u s ed a s n e ga ti v e full scale occu r s ? l s b be f o r e th e f i r s t cod e tra n si ti o n . p o si ti v e f u l l s c al e is def i ned as a lev e l 1 ? ls bs b e yo nd the las t cod e tra n si ti o n . t h e devia t i o n i s m e as u r ed f r o m th e m i d d le o f eac h p a r t ic u l a r co de t o t h e tr ue s t ra ig h t l i n e . max i mu m c o n v er si on r a te the clo c k ra t e a t w h ich p a ram e t r ic t e st in g is p e r f o r m e d . minim u m c o n v ersi on r a t e the clo c k ra t e a t w h ich t h e snr o f t h e lo w e s t a n alog sig n al f r e q u e nc y d r op s b y no more t h an 3 d b b e l o w t h e g u ar an te e d limi t. off s et e r r o r t h e ma jo r ca r r y tra n si tio n sh o u ld o c cur f o r a n a n alog val u e ? ls b b e lo w vi n+ = vin?. of fs et er r o r is def i n e d as t h e d e vi a t i o n o f th e a c t u al tra n s i ti o n f r o m th a t po in t . ou t- o f -r a n ge r e co v e r y t i m e t h e tim e i t tak e s f o r th e a d c t o r e a c q u i r e th e a n alog i n p u t a f t e r a tra n si ti o n f r o m 10% a b o v e pos i ti v e full s c ale t o 10% a b o v e n e ga t i v e f u l l s c ale , o r f r o m 10% b e lo w nega ti ve f u l l s c al e t o 10% be lo w p o si ti v e f u l l s c ale. ou t p u t p r o p ag a t i o n dela y (t pd ) t h e d e la y bet w e e n t h e c l oc k ri s i n g ed g e a n d t h e ti m e w h en all b i ts a r e wi thin valid log i c lev e ls. po w e r - s u p p l y r e j e c t i o n r a t i o th e cha n g e in f u l l s c ale f r o m t h e val u e wi t h t h e s u p p ly a t t h e minim u m limi t t o t h e va l u e wi t h t h e su p p l y a t i t s max i m u m limi t. s i g n a l -t o-n o is e an d dis t o r t i o n (s in ad) the ra t i o o f t h e r m s in p u t sig n a l a m pli t ude t o t h e r m s val u e o f th e s u m o f all o t h e r s p ectral co m p o n en t s be lo w th e n y q u i s t f r eq uen c y , in cl udin g ha r m o n ics b u t exc l udin g dc. s i g n a l -t o-n o is e r a ti o (s nr) the ra t i o o f t h e r m s in p u t sig n a l a m pli t ude t o t h e r m s val u e o f th e s u m o f all o t h e r s p ectral co m p o n en t s be lo w th e n y q u i s t f r e q uen c y , exc l u d in g t h e f i rs t six ha r m o n ics and dc. s p uri o us-f r e e d y na mi c r a n g e (s fd r) the ra t i o o f t h e r m s sig n al a m pl i t ude t o t h e r m s val u e o f t h e p e ak sp ur io us s p ec t r al co m p onen t. the p e a k s p ur io us co m p o - n e n t ma y o r m a y n o t be a ha r m o n ic. m a y be r e po r t ed in d b c ( i .e., deg r ades a s sig n a l le vel is l o w e r e d) o r dbf s ( a lwa y s r e l a te d b a ck t o con v er ter f u l l s c ale). t e m p er a t ure d r ift the t e m p er a t ure dr if t fo r o f fs et er r o r a n d ga in er r o r s p e c if ies t h e maxi m u m cha n g e f r o m t h e ini t ial (25c) va l u e t o t h e v a l u e at t min or t max . t o t a l ha r m on i c d i s t or t i on ( t h d ) the ra t i o o f t h e r m s in p u t sig n a l a m pli t ude t o t h e r m s val u e o f th e s u m o f th e f i r s t s i x h a rm o n ic co m p o n en t s . tw o - t o n e s f d r the ra t i o o f t h e r m s val u e o f ei t h er i n p u t t o n e to t h e r m s val u e o f t h e p e a k s p ur io us co m p on en t . th e p e ak s p ur io us co m p on en t ma y o r ma y n o t b e an imd p r o d uc t.
ad9444 rev. 0 | page 10 of 40 pin conf igurations and f u ncti on descriptions 26 27 28 29 30 55 54 53 52 51 top view (not to scale) ad9444 av dd1 av dd1 av dd2 av dd2 av dd2 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 av dd2 agnd c1 av dd1 av dd1 clk+ clk ? av dd1 av dd2 av dd2 av dd1 av dd1 (ls b ) d0 ? d0 + d1 ? d1 + drv dd drgnd d2 ? d2 + 80 d 13? 79 d 12+ 78 d 12? 77 d 11+ 76 d 11? 75 drvdd 74 drgnd 73 d10+ 72 d10? 71 d9+ 70 d9? 69 d8+ 68 d8? 67 drgnd 66 d7+ 65 d7? 64 dco+ 63 dco? 62 drvdd 61 drgnd 60 d6+ 59 d6? 58 d5+ 57 d5? 56 d4+ d4? drvdd drgnd d3+ d3? 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dcs mode agnd av dd1 agnd agnd av dd1 av dd1 av dd1 av dd1 av dd1 av dd1 av dd1 agnd av dd1 agnd or+ or? drv dd drgnd d 13+ ( m sb ) avdd1 dnc dnc dnc output mode dfs lvdsbias avdd1 avdd1 sense vref agnd reft refb agnd avdd1 avdd1 avdd1 avdd2 agnd vin+ vin? agnd avdd1 avdd1 05089-004 dnc = do not connect f i g u re 4. 10 0-l e ad t qfp/e p p i n co nf ig ur at i o n in l v ds m o de
ad9444 rev. 0 | page 11 of 40 table 7. pin function descriptions 100-lead tqfp/ep in lvds mode pin no. mnemonic description 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 avdd1 3.3 v (5%) analog supply. 2 to 4 dnc do not connect. these pins should float. 5 output mode cmos compatible output logic mode control pin. output mode = 0 for cmos mode, and output mode = 1 (avdd1) for lvds outputs. 6 dfs data format select pin. cmos control pin that determines the format of the output data. dfs = high (avdd1) for twos comple- ment, dfs = low (ground) for offset binary format. 7 lvdsbias set pin for lvds output current. place 3.7 k? resistor terminated to drgnd. 10 sense reference mode selection. connect to agnd for internal 1 v reference, and connect to avdd2 for external reference. 11 vref 1.0 v reference i/ofunction dependent on sense. decouple to ground with 0.1 f and 10 f capacitors. 12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, exposed heat sink agnd analog ground. the exposed heat sink on the bottom of the package must be connected to agnd. 13 reft differential reference output. decoupled to ground with 0.1 f capacitor and to refb (pin 14) with 0.1 f and 10 f capacitors. 14 refb differential reference output. decoupled to ground with a 0.1 f capacitor and to reft (pin 13) with 0.1 f and 10 f capacitors. 19, 28 to 31, 39 to 40 avdd2 5.0 v analog supply (5%). 21 vin+ analog inputtrue. 22 vin? analog inputcomplement. 33 c1 internal bypass node. connect a 0.1 f capacitor from this pin to agnd. 36 clk+ clock inputtrue. 37 clk? clock inputcomplement. 43 d0? (lsb) d0 complement output bit (lvds levels). pin no. mnemonic description 44 d0+ d0 true output bit. 45 d1? d1 complement output bit. 46 d1+ d1 true output bit. 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (3.0 v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd digital ground. 49 d2? d2 complement output bit. 50 d2+ d2 true output bit. 51 d3? d3 complement output bit. 52 d3+ d3 true output bit. 55 d4? d4 complement output bit. 56 d4+ d4 true output bit. 57 d5? d5 complement output bit. 58 d5+ d5 true output bit. 59 d6? d6 complement output bit. 60 d6+ d6 true output bit. 63 dco? data clock outputcomplement. 64 dco+ data clock outputtrue. 65 d7? d7 complement output bit. 66 d7+ d7 true output bit. 68 d8? d8 complement output bit. 69 d8+ d8 true output bit. 70 d9? d9 complement output bit. 71 d9+ d9 true output bit. 72 d10? d10 complement output bit. 73 d10+ d10 true output bit. 76 d11? d11 complement output bit. 77 d11+ d11 true output bit. 78 d12? d12 complement output bit. 79 d12+ d12 true output bit. 80 d13? d13 complement output. 81 d13+ (msb) d13 true output bit. 84 or? out-of-range complement output bit. 85 or+ out-of-range true output bit. 100 dcs mode clock duty cycle stabilizer (dcs) control pin, cmos-compatible. dcs = low (agnd) to enable dcs (recommended). dcs = high (avdd1) to disable dcs.
ad9444 rev. 0 | page 12 of 40 26 27 28 29 30 55 54 53 52 51 top view (not to scale) ad9444 av dd1 av dd1 av dd2 av dd2 av dd2 5 4 3 2 7 6 9 8 1 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 25 32 33 34 35 36 38 39 40 41 42 43 44 45 46 47 48 49 50 31 37 av dd2 agnd c1 av dd1 av dd1 clk+ clk? av dd1 av dd2 av dd2 av dd1 av dd1 dnc dnc dnc dnc drv dd drgnd dnc dnc 80 79 78 77 76 75 drvdd 74 drgnd 73 d6 72 d5 71 d4 70 d3 69 d2 68 d1 67 drgnd 66 d0 (lsb) 65 dnc 64 dco+ 63 dco? 62 drvdd 61 drgnd 60 dnc 59 dnc 58 dnc 57 dnc 56 dnc dnc drvdd drgnd dnc dnc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 avdd1 dnc dnc dnc output mode dfs dnc avdd1 avdd1 sense vref agnd reft refb agnd avdd1 avdd1 avdd1 avdd2 agnd vin+ vin ? agnd avdd1 avdd1 05089-005 dnc = do not connect dcs mode agnd av dd1 agnd agnd av dd1 av dd1 av dd1 av dd1 av dd1 av dd1 av dd1 agnd av dd1 agnd or d 13 ( m s b ) drv dd drgnd d1 2 d1 1 d1 0 d9 d8 d7 f i g u re 5. 10 0-l e ad t qfp/e p p i n co nf ig ur at i o n in c m os m o de
ad9444 rev. 0 | page 13 of 40 table 8. pin function descriptions100-lead tqfp/ep in cmos mode pin no. mnemonic description 1, 8 to 9, 16 to 18, 24 to 27, 34 to 35, 38, 41 to 42, 87, 89 to 95, 98 avdd1 3.3 v (5%) analog supply. 2 to 4, 7, 43 to 46, 49 to 52, 55 to 60, 65 dnc do not connect. these pins should float. 5 output mode cmos compatible output logic mode control pin. output mode = 0 for cmos mode, and output mode = 1 (avdd1) for lvds outputs. 6 dfs data format select pin. cmos control pin that de- termines the format of the output data. dfs = high (avdd1) for twos comple- ment, dfs = low (ground) for offset binary format. 10 sense reference mode selection. connect to agnd for internal 1 v reference, and connect to avdd2 for external reference. 11 vref 1.0 v reference i/o function dependent on sense. decouple to ground with 0.1 f and 10 f capacitors. 12, 15, 20, 23, 32, 86, 88, 96 to 97, 99, exposed heat sink agnd analog ground. the exposed heat sink on the bottom of the package must be connected to agnd. 13 reft differential reference out- put. decoupled to ground with 0.1 f capacitor and to refb (pin 14) with 0.1 f and 10 f capacitors. 14 refb differential reference out- put. decoupled to ground with a 0.1 f capacitor and to reft (pin 13) with 0.1 f and 10 f capacitors. 19, 28 to 31, 39 to 40 avdd2 5.0 v analog supply (5%). 21 vin+ analog inputtrue. 22 vin? analog inputcomplement. pin no. mnemonic description 33 c1 internal bypass node. connect a 0.1 f capacitor from this pin to agnd. 36 clk+ clock inputtrue. 37 clk? clock inputcomplement. 47, 54, 62, 75, 83 drvdd 3.3 v digital output supply (2.5v to 3.6 v). 48, 53, 61, 67, 74, 82 drgnd digital ground. 63 dco? data clock output complement (cmos levels). 64 dco+ data clock output true. 66 d0 (lsb) d0 output bit (lsb) (cmos levels). 68 d1 d1 output bit. 69 d2 d2 output bit. 70 d3 d3 output bit. 71 d4 d4 output bit. 72 d5 d5 output bit. 73 d6 d6 output bit. 76 d7 d7 output bit. 77 d8 d8 output bit. 78 d9 d9 output bit. 79 d10 d10 output bit. 80 d11 d11 output bit. 81 d12 d12 output bit. 84 d13 (msb) d13 output bit. 85 or out-of-range output. 100 dcs mode clock duty cycle stabilizer (dcs) control pin, cmos- compatible. dcs = low (agnd) to enable dcs (recommended). dcs = high (avdd1) to disable dcs.
ad9444 rev. 0 | page 14 of 40 equivalent circuits x1 avdd2 3.5v 1k ? 1k ? avdd2 vin+ vin ? sha avdd2 05089-006 2.5pf 2.5pf f i g u re 6. equ i v a l e n t a n al og input c i rc uit 05089-007 1.2v drvdd drvdd k 3.74k ? i lvdsout lvdsbias f i gure 7. equ i v a l e n t l v ds bia s c i rcuit dr vdd dx? dx+ v v v v 05089-008 f i gure 8 . e q ui v a lent l v ds di g i tal o u tp ut ci rcui t dx dr vdd 05089-009 f i gure 9 . e q u i v a len t c m os di gi tal o u t p ut ci rcui t dcs m o de , o u t p u t mo d e , df s vd d 30k ? 05089-010 f i gure 1 0 . e q ui v a l e nt di gi tal input circui t, dfs, dcs mo de, o u tput mode clk+ 12k ? 10k ? 150 ? 150 ? 12k ? 10k ? a v dd 2 clk? 05089- 011 f i gure 11. equiv a le nt s a mpl e c l o c k in put circuit
ad9444 rev. 0 | page 15 of 40 typical perf orm ance cha r acte ristics a v d d 1 = 3.3 v , a v d d 2 = 5.0 v , d r vd d = 3.3 v , s a m p le ra t e = 80 ms ps, l v ds m o de , d c s ena b led , t a = 25c, 2 v p-p dif f er en t i al in p u t, ai n = ?0.5 dbfs, in t e r n a l t r imm e d r e fer e n c e (n omina l vref = 1.0 v), unless o t h e r w is e n o t e d. ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-012 80msps 10.1mhz @ ? 0.5dbfs snr: 73.9db enob: 12.0bits sfdr: 97dbc 0 f i g u re 12. 6 4 k p o in t sing l e - t one ff t/ 8 0 m s ps/ 10. 1 m h z ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-013 80msps 30.3mhz @ ? 0.5dbfs snr: 74.0db enob: 12.1bits sfdr: 95dbc 0 f i g u re 13. 6 4 k p o in t sing l e - t one ff t/ 8 0 m s ps/ 30. 3 m h z ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-014 80msps 70.3mhz @ ? 0.5dbfs snr: 73.3db enob: 11.9bits sfdr: 100dbc 0 f i gur e 1 4 . 64 k p o i n t si ngle- t o n e fft/80 msp s /7 0 mhz ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-015 80msps 100.3mhz @ ? 0.5dbfs snr: 72.3db enob: 11.8bits sfdr: 96dbc 0 f i gur e 1 5 . 64 k p o i n t si ngle- t o n e fft/80 msp s /1 00 m h z ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-016 0 80msps 125mhz @ ? 0.5dbfs snr: 71.2db enob: 11.6bits sfdr: 91dbc f i gur e 1 6 . 64 k p o i n t si ngle- t o n e fft/80 msp s /1 25 m h z ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-017 80msps 151mhz @ ? 0.5dbfs snr: 71.1db enob: 11.5bits sfdr: 87dbc 0 f i gur e 1 7 . 64 k p o i n t si ngle- t o n e fft/80 msp s /1 51 m h z
ad9444 rev. 0 | page 16 of 40 65 66 67 68 69 70 71 72 73 74 75 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 analog input frequency (mhz) (db) 05089-018 snr db @ +85 c snr db @ ? 40c snr db @ +25c f i g u re 18. snr v s . a n al og input f r eque nc y , 80 m s ps /l v d s m o de 05089-019 70 75 80 85 90 95 105 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 analog input frequency (mhz) (db) sfdr dbc @ +85c sfdr dbc @ +25c 100 sfdr dbc @ ? 40c f i g u re 19. sfdr v s . a n al og input f r equ e nc y , 8 0 m s ps/l v d s m o de 10 20 30 40 50 60 70 80 90 100 110 120 ?100 ? 9 0 ? 80 ? 7 0 ? 60 ? 5 0 ? 40 ?30 ? 20 ?10 0 analog input amplitude (dbc) (db) 05089-020 third ?dbfs second ?dbfs sfdr ?dbfs third ?dbc second ?dbc sfdr ?dbfs f i gure 20. sing le - t one sfdr/s econd/thir d vs. a n al og input l e vel , 80 m s p s , a in = 3 0 . 3 mh z 05089-021 65 66 67 68 69 70 71 72 73 74 75 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 analog input frequency (mhz) (db) snr db @ +85c snr db @ ? 40 c snr db @ +25 c f i g u re 21. snr v s . a n al og input f r eque nc y , 80 m s ps /c m o s m o de 05089-022 0 2 0 4 0 6 0 8 0 100 120 140 160 180 200 analog input frequency (mhz) sfdr dbc @ +25 c sfdr dbc @ ? 40c sfdr dbc @ +85c 70 75 80 85 90 95 100 105 (db) f i g u re 22. sfdr v s . a n al og input f r equ e nc y , 8 0 m s ps/c m o s m o de 05089-023 10 20 30 40 50 60 70 80 90 100 110 120 ?100 ?90 ? 80 ?70 ? 60 ?50 ? 40 ?30 ? 20 ?10 0 analog input amplitude (dbc) (db) third ?dbfs second ? dbfs sfdr ?dbfs third ?dbc second ?dbc sfdr ?dbfs f i gure 23. sing le - t one sfdr/s econd/thir d vs. a n al og input l e vel 80 m s ps, a in = 7 0 .3 0 mh z
ad9444 rev. 0 | page 17 of 40 ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-024 0 sfdr: 102dbfs f i gure 24. 3 2 k p o in t t w o - t o n e fft 8 0 msps/ 9 . 8 mh z/ 10 . 8 mh z ? 120 ? 100 ?80 ?60 ?40 ?20 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089-025 0 ? 110 ?90 ?70 ?50 ?30 ?10 sfdr: ? 100dbfs f i gur e 2 5 . 32 k p o i n t t w o - t o ne fft 80 msp s /6 9.3 m h z/ 70.3 m h z 70 75 80 85 90 95 100 20 30 40 50 60 70 80 90 100 110 sample rate (msps) s f dr (db) 05089-026 f i gure 26. sfdr vs. s a mple rate , v in = 10. 3 m h z @ ? 0 .5 d b fs ? 120 ? 100 ?80 ?60 ?40 ?20 imd (dbfs ) 05089-027 0 ? 110 ?90 ?70 ?50 ?30 ?10 ?110 ? 100 ?90 ? 80 ? 7 0 ? 60 ?50 ? 40 ?30 ? 20 ?10 0 analog input level (dbfs) worst third-order imd (dbfs) sfdr (dbfs) worst third-order imd (dbc) 90dbfs reference line sfdr (dbc) f i gure 27. t w o - t o n e sfdr v s . a n al og i n put l e vel , a in = 9 . 8 m h z/ 10. 8 m h z ? 120 ? 100 ?80 ?60 ?40 ?20 s f dr and imd3 (db) 05089-028 0 ? 110 ?90 ?70 ?50 ?30 ?10 ?110 ? 100 ?90 ? 80 ? 7 0 ? 60 ?50 ? 40 ?30 ? 20 ?10 0 analog input level (dbfs) worst third-order imd (dbfs) sfdr (dbfs) worst third-order imd (dbc) 90dbfs reference line sfdr (dbc) f i gure 28. t w o - t o n e sfdr v s . a n al og i n put l e vel , a in = 6 9 . 3 m h z/ 70 .3 m h z 70 75 80 85 90 95 100 10 20 30 40 50 60 70 80 90 100 110 sample rate (msps) s f dr (db) 05089-029 f i gure 29. sfdr vs. s a mple rate , v in = 70. 3 m h z @ ? 0 .5 d b fs
ad9444 rev. 0 | page 18 of 40 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 7.68 15.36 23.04 30.72 frequency (mhz) amp l itude (dbfs ) 05089-030 61.44msps total input signal power: ?30dbfs f i g u re 30. 6 4 k fft , 61. 4 4 m s p s , 4 @ w c dm a, if = 4 6 .0 8 m h z ?130 ?120 ?110 ?100 ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 0 5 10 15 20 25 30 35 40 frequency (mhz) amp l itude (dbfs ) 05089 ?031 npr: 63.1db f i gur e 3 1 . np r, 80 msp s /1 8 mh z no t c h 05089-032 70 75 80 85 90 95 100 105 20 30 40 50 60 70 80 clock duty cycle (%) db sfdr - dcs off (dbfs) sfdr - dcs on (dbfs) snr - dcs off (db) snr - dcs on (db) f i gure 32. sing le - t one snr/sfdr vs. clock d u t y c y c l e , f sa mple = 8 0 m s ps, 10. 3 m h z @ ? 0 .5 d b fs 05089-033 0 2000 4000 6000 8000 10000 12000 8179 8180 8181 8182 8183 8184 8185 8186 8187 b in fre q ue ncy f i g u re 33. ground i n put his t og r a m 80 m s ps, v i n+ = v i n?, 32 k s a mpl e s 05089-034 50 70 90 110 130 150 170 190 210 230 250 20 30 40 50 60 70 80 90 100 110 120 130 sample rate (msps) curre nt (ma) avdd1 (3.3v) avdd2 (5.0v) drvdd (3.3v) f i g u re 34. i su ppl y vs. s a mple rate , a in = 10. 3 m h z @ ? 0 .5 d b fs 60 65 70 75 80 85 90 95 100 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 v in common-mode (v) (db) 05089-035 sfdr (dbc) snr (db) f i gure 35. sing le - t one snr/sfdr vs. v in co mm on-m ode v o lt ag e 80 m s ps /1 0.3 m h z
ad9444 rev. 0 | page 19 of 40 05089-036 0.951 0.952 0.953 0.954 0.955 0.956 0.957 0.958 0.959 0.960 0.961 ? 2 0 0 20 40 60 80 temperature (c) re fe re nce v o ltage (v ) ?4 0 f i gure 36. vr e f v s . t e m p er ature ? 1.00 ? 0.75 ? 0.50 ? 0.25 0 0.25 0.50 0.75 1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 output code dnl e rror (ls b ) 05089-037 f i gure 37. dnl e r ro r v s . o u tput code , 80 m s ps, a in = 1 5 mh z 05089-038 ? 2 0 0 20 40 60 80 temperature (c) ?40 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 gain ( % fs) f i gure 38. g a in v s . t e m p er ature ? 1.00 ? 0.75 ? 0.50 ? 0.25 0 0.25 0.50 0.75 1.00 0 2048 4096 6144 8192 10240 12288 14336 16384 output code inl e rror (ls b ) 05089-039 f i gure 39. inl er r o r vs. o u tput c o de , 80 ms ps, a in = 1 5 m h z
ad9444 rev. 0 | page 20 of 40 theory of operation the ad9444 a r c h i t ec t u r e is o p t i mize d f o r hig h s p ee d an d eas e o f us e . th e a n alog in p u ts dr i v e a n in t e g r a t e d , hig h ban d wid t h, tra c k - a n d - h o ld ci r c u i t th a t s a m p le s th e s i gn al p r i o r t o q u a n tiz a - t i o n b y t h e 14- b i t pi p e l i n e a d c co r e . th e de vic e in cl udes an on - b o a rd re f e re nc e a n d i n put l o g i c t h a t a c c e pt s t t l , c m o s , or l v p e cl leve ls. the dig i tal o u t p u t log i c lev e ls a r e us er s e lec t a b le as s t anda rd 3 v cm os o r l v ds (ans i-644 com p a t i b le) via t h e outp u t mode pi n. analog input and re ference overview a s t a b le an d acc u ra t e 0.5 v v o l t a g e r e fer e n c e is b u i l t i n t o t h e ad9444. th e in p u t ra n g e ca n b e ad j u s t ed b y var y in g th e r e f e r - en c e v o l t a g e a p p l ied t o t h e ad9444, usin g ei ther th e in t e r n al re f e re nc e or an e x te r n a l ly a p pl i e d re f e re nc e vo lt age. t h e i n put sp an of t h e a d c t r a c k s re fe re n c e volt age ch an ge s l i ne arly . t h e va r i o u s r e fer e n c e m o des a r e des c r i b e d in t h e n e x t fe w s e c t ion s . i n te rna l re fere nce conne c tion a co m p a r a t o r wi t h in t h e ad9 444 det e c t s t h e p o t e n t ial a t t h e s e ns e pin and co nf igur es t h e refer e n c e i n t o fo ur p o s s i b le s t a t es, w h ich a r e s u mma r i ze d i n t a b l e 9. i f s e ns e is g r o u nde d , t h e r e fer e n c e am plif ier s w i t ch is co nne c t e d t o t h e i n t e r n a l r e sis- to r divider ( s e e f i gur e 40) , s e t t i n g vref to ~1 v . c o nn e c t i n g t h e s e ns e pin to vref sw i t ch e s t h e r e fer e nce am plif ier o u t p u t t o th e s e n s e p i n , co m p le tin g t h e loo p a n d p r o v i d i n g a ~0.5 v re f e re nc e output . i f a re s i stor d i v i d e r i s c o n n e c t e d, a s s h ow n i n f i gur e 41, th e s w i t c h a g a i n s e ts t o th e s e ns e p i n. this p u ts t h e re fe re nc e a m pl i f i e r i n a non i n v e r t i ng mo d e w i t h t h e v r e f o u t p ut def i n e d as ? ? ? ? ? ? + = r1 r2 vref 1 0.5 i n a l l r e fer e n c e co nf igur a t io n s , ref t an d ref b dr i v e t h e a / d co n v ersio n co r e a nd es t a b l is h i t s in p u t s p a n . the in p u t ra n g e o f t h e ad c alwa ys e q uals t w ic e t h e v o l t a g e a t t h e r e fer e n c e p i n fo r ei t h er a n i n t e r n al o r a n ext e r n al r e fer e n c e . i n te rna l re fere nce tr im the i n t e r n al r e fer e n c e v o l t a g e i s t r imm e d d u r i n g t h e p r o d uc - ti o n t e s t t o a d j u s t th e g a i n (a n a log i n p u t v o l t a g e ra n g e ) o f th e ad9444. th er ef o r e , th er e is li t t le ad van t a g e t o t h e us er s u p p ly- in g a n exter nal v o l t a g e r e fer e n c e t o t h e ad944 4. th e gain t r i m is p e r f o r m e d wi th the ad9444 s in p u t ran g e s e t t o 2 v p-p n o m i na l ( s en se co nn e c te d to a g nd) . b e c a us e o f t h is t r im, a nd b e c a us e t h e 2 v p-p a n alog in p u t ra n g e p r o v ides maxim u m ac p e r f o r ma n c e , t h er e is li t t le b e n e f i t t o usin g analog in p u t ra n g es < 2 v p- p . u s ers a r e c a u t io n e d t h a t t h e dif f er en t i al n o nl ine a r i ty o f t h e ad c va r i es wi t h t h e r e fer e nce v o l t a g e . c o nf igura t io n s t h a t us e < 2 v p - p ma y exhib i t mis s in g co des an d, t h e r e f ore, d e g r a d e d noi s e a n d d i s t or t i on p e r f o r m a nc e. 10 f + 0.1 f vref sense 0.5v ad9444 vin? vin+ reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + 05089- 043 f i gure 40. inte rn al r e fer e n c e configu r atio n 05089- 042 10 f + 0.1 f vref sense r2 r1 0.5v ad9444 vin? vin+ reft 0.1 f 0.1 f 10 f 0.1 f refb select logic adc core + f i g u re 41. p r og r a m m ab le r e f e rence conf ig ur at i o n
ad9444 rev. 0 | page 21 of 40 ta ble 9. r e fere nce co nfi g ura t i o n sum m a r y selected mode sense voltage resulting vref (v) resulting di ffe rential span ( v p-p) external reference avdd n/ a 2 external reference internal fixed reference vref 0.5 1.0 programmable reference 0.2 v to v r ef ? ? ? ? ? ? + r1 r2 1 0.5 (see figure 41) 2 vref internal fixed reference agnd to 0.2 v 1.0 2.0 extern al r e f e r e nc e ope r atio n the ad9444 s in t e r n al r e f e r e n c e is tr immed t o enhan c e t h e gain acc u rac y o f t h e ad c. a n ext e r n al r e fer e n c e ma y b e m o r e s t a b l e o v er t e m p era t ure , b u t t h e ga i n of t h e a d c is n o t li k e ly t o b e i m prove d . f i g u r e 3 6 show s t h e t y pi c a l d r i f t ch ar a c te r i st i c s of t h e in ter n a l r e fer e nce in b o t h 1 v and 0.5 v m o des. w h en t h e s e nse p i n is t i e d t o a v d d , t h e i n te r n al r e fer e n c e is dis a b l e d , al lo wi n g t h e us e o f a n ext e r n al r e fer e n c e . a n i n t e r n al r e fer e n c e b u f f er lo ads t h e ext e r n al r e fer e n c e wi t h a n e q ui vale n t 7 k? lo ad . the i n t e r n al b u f f er s t i l l g e n e r a t e s t h e p o si t i v e and n e g a t i ve f u l l -s c a le r e fer e n c es, r e ft an d refb , fo r t h e ad c co r e . the in p u t s p a n is alw a ys t w ice t h e val u e of t h e r e fer e n c e v o l t a g e; t h er efo r e , t h e ext e r n al refer e n c e m u s t b e limi t e d t o a max i m u m o f 1 v . analog inputs a s wi t h m o s t ne w hig h sp e e d , hig h d y na mic r a n g e a d cs, t h e a n alog in p u t t o th e ad9444 is dif f er en tial . dif f er en tial in p u ts i m prove on - c h i p p e r f or m a nc e a s s i g n a l s are pro c e s s e d t h rou g h a t t e n u a t io n and ga in s t a g es. m o s t o f t h e i m p r o v em e n t is a r e s u lt of d i f f e r e n t i a l a n a l o g st age s h a v i ng h i g h re j e c t i o n of e v e n - ord e r ha r m o n ics. the r e a r e als o b e n e f i ts a t t h e pcb l e v e l. f i rst, dif f er en t i al in puts ha v e hig h comm on- m o d e r e je c t io n o f s t r a y sig n a l s, such as g r o u n d and p o w e r n o is e. s e cond , t h e y p r o v id e g o o d r e jec t ion o f co mm on-m o d e sig n als, s u c h as lo cal os cil l a t or f eed thr o u g h . the s p ecif ie d n o is e a nd dis t o r tio n o f th e ad9444 ca n n o t b e r e a l i z e d wi t h a sing le -ende d a n a l o g i n p u t, s o such co nf igura t io n s a r e dis c o u ra ge d . c o n t ac t ad i fo r r e co mm e n d a - t i ons of ot he r 1 4 - b it a d c s t h a t supp or t s i ng l e - e nd e d a n a l o g in p u t co nf igura t io n s . w i t h t h e 1 v r e fer e n c e ( n o m ina l val u e , s e e t h e i n t e r n al r e fer - en c e t r im s e c t io n), th e dif f er en tial in p u t ra n g e o f th e ad9444 s a n alog in p u t is n o minal l y 2 v p-p o r 1 v p-p o n eac h in p u t (vin + o r vin ? ). 3.5v vi n + vi n ? 1vp-p digit al out = all 1s digit al out = all 0s 05089-045 f i gure 4 2 . di ffer e nt i a l a n al o g input range fo r vref = 1 v the ad9444 a n alog in p u t v o l t ag e ra n g e is o f fs et f r o m g r o u n d b y 3.5 v . e a c h a n alog in p u t co nn ec ts thr o u g h a 1 k? r e sis t o r t o t h e 3.5 v b i as vol t a g e and t o t h e in p u t o f a dif f er en t i a l b u f f er . the i n t e r n al b i as n e tw o r k on t h e in p u t p r o p erly b i as es t h e b u f f er fo r maxi m u m li n e a r i t y and ra n g e (s e e t h e e q ui valen t cir c ui ts s e c t ion). th er efo r e , t h e a n alog s o ur ce dr i v in g t h e ad9444 sh o u ld be ac -co u p l ed to th e in p u t p i n s . the r e co m- m e n d ed m e t h o d f o r dr i v in g t h e a n alog in p u t of th e ad9444 is t o us e a n rf t r an sfo r m e r t o co n v er t sin g le-e n d e d sig n als t o d i f f e r e n ti al (s ee f i g u r e 44). s e ri e s r e s i s t o r s be tw ee n t h e o u t p u t o f th e tra n sf o r m e r and the ad9444 a n alog in p u ts he l p is ol a te th e a n alog i n p u t so ur ce f r o m sw i t c h in g tra n s i en t s ca use d b y th e i n te r n a l s a m p l e - a nd - h o l d c i rc u i t . t h e s e r i e s re s i stor s , a l ong w i t h th e 1 k? r e sis t ers co nn ec t e d t o th e in t e r n al 3.5 v b i as, m u st b e co n s ider e d i n i m p e dance ma t c hin g t h e t r a n sfor m e rs in p u t. f o r exa m ple , if r t w e r e s et t o 51 ? and r s w e r e s et to 33 ?, alo n g w i t h a 1: 1 i m pe d a n c e ra ti o tra n s f o r m e r , th e i n p u t w o uld ma t c h a 50 ? s o ur ce wi th a f u l l -s cale dr i v e o f 10.0 db m. th e 50 ? im p e dan c e ma tchin g c a n als o b e inco r p o r a t e d o n t h e s e conda r y s i d e o f th e tra n sf o r m e r , a s s h o w n i n t h e ev al ua tio n boa r d sch e - ma tic (s ee f i gur e 47 a nd f i gur e 59). 05089-046 0.1 f r t ad9444 ain ain r s r s adt1? 1wt analog input signal f i gur e 4 3 . t r a n sform e r - c o upl e d a n alo g input ci r c ui t
ad9444 rev. 0 | page 22 of 40 clock inpu t consider ations an y hig h s p e e d ad c is ext r e m ely s e n s i t i v e t o t h e q u al i t y o f t h e sa m p li n g c l oc k p r o v i d ed b y t h e use r . a tra c k - a n d - h o ld ci r c ui t i s e s s e n t i a l l y a m i x e r , and a n y noi s e, d i stor t i on , or t i m i ng j i tt e r on th e c l ock i s co m b in e d w i t h th e d e s i r e d s i gn al a t th e a / d o u t p u t . f o r t h a t re a s on , c o ns i d e r abl e c a re w a s t a ke n i n t h e d e s i g n of t h e c l o c k in p u ts o f th e ad9444, and th e us er is advis e d t o g i ve c a re f u l t h ou g h t to t h e cl o c k s o u r c e . t y p i cal h i g h s p eed a d c s us e b o th c l oc k e d g e s t o g e n e ra t e a va r i ety o f in t e r n al timing sig n als a n d , as a r e s u l t , ma y be s e n s i t i v e t o t h e clo c k d u ty c y cle . c o mm o n ly a 5 % t o leran c e is r e q u ir e d o n t h e clo c k d u ty c y cle t o ma in t a i n d y na mic p e r f o r m- anc e ch ar a c te r i s t i c s . t h e a d 9 4 4 4 c o n t ai ns a cl o c k d u t y c y cl e s t a b i l i z er (d cs) t h a t r e t i m e s t h e n o n s a m pl in g e d g e , p r o v idin g a n in t e rn al c l ock si gn al w i t h a n o mi n a l 50% d u ty c y c l e . a s sh own i n f i gur e 32, n o is e and di sto r t i o n p e r f o r ma nce a r e n e a r ly f l a t fo r a 30% t o 70% d u ty c y cle wi t h t h e d c s e n a b le d . the d c s cir c ui t lo cks t o t h e r i sin g e d g e of clk+ an d o p t i mi zes t i min g in t e r n a l ly . this a l lo ws fo r a wide ra n g e o f in pu t d u ty c y cles a t t h e i n p u t w i t h ou t deg r adin g p e r f o r ma n c e . j i t t e r in t h e r i sin g e d g e o f t h e in p u t is s t i l l o f p a ra m o u n t con c er n a nd is n o t r e - d u ce d b y t h e i n ter nal s t a b i l iza t i o n cir c ui t. the d u ty c y cle co n - tr o l lo o p do es no t f u n c tio n f o r c l o c k ra t e s les s t h a n 30 m h z n o mi n a ll y . th e loo p h a s a tim e co n s ta n t as soci a t ed wi th i t th a t n e e d s t o b e co nsider e d i n a p pli c a t ion s w h er e t h e clo c k ra te can c h a n g e dyna mical l y , whic h r e q u ir es a wa i t time o f 1.5 s t o 5 s a f t e r a d y na mic c l o c k f r eq uen c y in cr eas e (o r de cr eas e ) bef o r e t h e d c s lo o p is r e lo ck e d t o t h e in p u t sig n al. d u r i n g t h e t i me p e r i o d t h e lo o p is n o t lo ck e d , t h e d c s lo o p is b y p a s s e d , and t h e in t e r n al de vice t i min g is dep e nda n t on t h e d u ty c y cle o f t h e in p u t clo c k sig n a l . i n such a n a pplica t ion, i t ma y a p p r o p r i a t e t o dis a b l e t h e d u ty c y cle s t a b i l i z er . i n al l o t h e r a p pl ica t ion s , ena b lin g t h e d c s cir c ui t is r e c o mmende d to max i mi ze ac pe rf o r m a n c e . the d c s c i r c ui t is co n t r o l l e d b y t h e d c s mod e p i n; a cmo s log i c lo w (a gnd) o n d c s mod e ena b les t h e d u ty c y cle s t ab i - lizer , an d log i c hig h (a vdd1 = 3.3 v) dis a b l es t h e con t r o l l er . the ad9444 in p u t s a m p le c l o c k sig n al m u st b e a hig h q u al i t y , ext r em e l y lo w phas e n o is e s o urce t o p r e v e n t de g r ada t io n o f p e r f o r ma n c e. m a in t a ini n g 14- b i t acc u rac y places a p r emi u m on t h e e n co de clo c k phas e n o is e . snr p e r f o r ma n c e can e a si ly deg r ade b y 3 db t o 4 db wi th 70 mh z analog in p u t sig n als when usin g a hig h ji t t e r c l o c k s o ur ce . (s ee an-501 , a p e r t u r e u n cer t a i n t y and a d c s y st em p e r f o r ma n c e , fo r co m p let e deta ils.) f o r o p tim u m p e r f o r ma n c e , t h e ad944 4 m u s t be clo c k e d dif f er en t i al ly . th e s a m p le clo c k in pu ts ar e in t e r n al ly b i as e d t o ~2.2 v , a n d t h e in p u t s i g n a l is usua l l y ac-co u ple d in t o th e cl k + a n d c l k ? p i n s via a tra n s f o r m e r o r ca pa ci t o r s . f i gur e 44 s h o w s o n e p r ef er r e d m e t h o d f o r c l o c kin g t h e ad944 4. the cl o c k s o u r c e ( l ow ji tte r ) i s c o n v e r te d f rom s i ng l e - e nd e d - t o - dif f er en t i al using a n rf t r a n sfo r m e r . th e b a ck- t o-b a ck s c h o t t k y dio d es acr o s s t h e t r a n sfo r m e r s e co nda r y limi t clo c k exc u rsio n s in t o t h e ad944 4 t o a p p r o x ima t e l y 0.8 v p-p dif f er en tial . this h e l p s p r e v e n t t h e la rg e v o l t a g e s w i n gs o f t h e clo c k f r o m fe e d ing thr o u g h t o o t h e r p o r t io n s o f th e ad9444 and limi ts t h e n o is e p r es en t e d t o t h e s a m p le clo c k in p u ts. i f a lo w ji t t er c l o c k is a v a i lab l e , a n o t h e r o p tio n is t o ac co u p le a dif f er en t i al e c l / p e cl sig n al t o t h e e n co de i n pu t p i n s , as sh o w n in f i gur e 46. 05089-047 0.1 f ad9444 clk+ clk ? hsms2812 diodes clock source adt1?1wt f i gure 44. cr ystal c l o c k o s ci ll ator , d i ff er e n tia l e n code 05089-048 0.1 f ad9444 encode encode 0.1 f vt vt ecl/ pecl f i gure 4 5 . di ffer e nt i a l ecl fo r enc o d e jitter considerations h i g h s p e e d , hig h r e s o l u t i o n ad cs a r e s e n s i t i v e t o t h e quali t y o f t h e clo c k i n pu t. th e deg r ada t io n i n s n r a t a g i v e n i n p u t fr e q u e n c y ( f inpu t ) a nd r m s a m pl i t ude d u e only t o a p er t u r e ji t t e r ( t j ) ca n be calcu l a t ed us i n g t h e fo llo w i n g eq ua tio n . snr = 20 log[2 t j ] i n t h e e q ua t i o n , t h e r m s a p er t u re ji t t er r e p r es e n ts t h e r o ot- m e a n s q ua r e o f al l ji t ter s o ur ces, w h ich i n cl udes t h e cl o c k i n p u t, a n alog in p u t sig n al, a nd a d c a p er t u r e ji t ter s p e c if ica t ion. if un ders am plin g a p plic a t ion s a r e p a r t ic u l a r ly s e n s i t i v e t o ji t t er , s e e f i gur e 46. the c l o c k in p u t s h o u ld be tr e a ted as an a n alog sig n al in c a s e s w h er e a p er t u r e ji t t er ma y a f fe c t t h e dyna mic ran g e o f t h e ad9444. p o w e r s u p p lies f o r c l o c k dr i v ers sh o u ld b e s e p a ra t e d f r o m t h e ad c o u t p ut dr i v er s u p p lies t o a v o i d m o d u l a t i ng t h e clo c k sig n al wi t h dig i t a l n o is e . l o w ji t ter , cr ys tal-co n t r o l l e d os cil l a t o r s ma k e th e bes t c l o c k s o ur ces. i f th e c l o c k is g e n e ra t e d f rom anot he r t y p e of s o u r c e ( b y g a t i n g , d i v i d i n g , or ot he r me t h - od s ) , i t s h o u ld b e r e ti m e d b y t h e o r i g i n al c l oc k a t th e la s t s t ep .
ad9444 rev. 0 | page 23 of 40 input frequency (mhz) s nr (dbc ) 1 40 75 70 65 60 55 50 45 1000 100 10 05089-049 0.2ps 0.5ps 1.0ps 1.5ps 2.0ps 2.5ps 3.0ps f i gure 4 6 . snr vs . input f r equenc y a n d j i tter p o wer co nsid erat io ns c a r e s h o u ld b e t a k e n w h en s e le c t in g a p o w e r s o ur ce . th e us e o f lin e a r dc s u p p lies is hig h l y r e co mmende d . s w i t c h in g s u p p lies t e nd t o ha v e radia t e d co m p o n en ts tha t ma y be r e cei v e d b y th e ad9444. e a c h of th e p o w e r s u p p l y p i n s sh o u ld be deco u p led as c l ose l y t o th e pac k a g e a s pos s i b le u s i n g 0 . 1 f c h i p ca pa c i t o r s . the ad9444 has s e p a ra t e dig i ta l a nd a n alog p o w e r s u p p l y p i n s . th e analog s u p p lies a r e den o te d a v d d 1 (3.3 v) a nd a v dd2 ( 5 v) and t h e dig i t a l sup p ly p i n s a r e de n o te d dr vdd . al th o u g h th e a v d d 1 a n d d r v d d s u p p li e s m a y b e ti e d t o g e t h er , b e st p e r f o r ma n c e is achie v e d w h e n t h e s u p p lies a r e s e p a ra t e . this is b e c a us e t h e f a st dig i t a l o u t p u t swi n gs can co u p le sw i t ching c u r r en t b a ck i n t o t h e a n alog su p p lies. n o t e th a t bo th a v d d 1 a n d a v d d 2 m u s t be h e ld wi th in 5% o f t h e sp e c if ie d v o l t a g e . the d r vdd s u p p l y o f th e ad9 444 is a dedic a ted s u p p l y f o r the dig i t a l o u t p u t s, i n ei t h er l v ds or cmos o u t p u t m o des. w h en in l v ds mo de , t h e dr vd d sho u ld b e s et t o 3. 3 v . i n cmos m o de , the d r vd d s u p p l y ma y be co nnec t e d f r o m 2.5 v t o 3.6 v t o be com p a t ib le wi th t h e r e cei v in g log i c. digi tal ou tputs lvds mo de the o f f-chi p dr i v ers o n t h e chi p ca n b e conf igur e d t o p r o v ide l v ds-com p a t i b l e o u t p u t leve ls via p i n 5 (o utput m o d e ). l v ds o u t p u t s ar e a v a i la b l e w h e n o u tp ut mo d e is cmos log i c hig h (o r a v d d 1 f o r co n v enien c e) and a 3.74 k? r set re s i stor i s pl a c e d a t p i n 7 ( l v d sbi a s ) to g rou n d . d y n a m i c p e r f o r ma n c e, i n cl udin g b o t h s f dr a nd snr , is max i mi ze d w h en t h e ad94 44 is us e d in l v ds mo de , and desig n ers a r e en co ura g ed t o tak e ad van t a g e of this m o de . the ad9444 o u t - p u ts i n cl ude com p li m e n t a r y l v ds o u t p u t s for e a ch da t a b i t (d x+/d x?), the o v er ra n g e o u t p u t (o r+/o r? ), a n d t h e o u t p u t da ta c l ock o u t p u t (d co +/d c o ? ). t h e r set re s i stor c u r r e n t i s ra t i o e d o n - c hi p , s e t t i n g t h e o u t p u t c u r r en t a t e a ch o u t p u t e q ual t o a n o minal 3. 5 ma (11 ). a 100 ? dif f er en tial t e r m ina - t i on re s i stor pl a c e d a t t h e l v d s re c e ive r i n put s re su lt s i n a n o minal 350 mv swin g a t t h e recei v er . l v ds m o de facil i ta t e s in t e r f acing w i t h l v ds r e cei v ers in c u st om a s ics an d fpg a s th a t ha v e l v d s c a pa b i l i t y f o r s u pe ri o r s w i t c h in g pe rf o r m a n c e in n o isy e n v i r o n m e n t s. si n g le p o in t-t o - p o i n t n et t o p o log i es a r e r e co mmen d e d wi t h a 100 ? t e r m ina t io n r e sis t o r as c l os e t o the r e cei v er as p o s s ib le . i t is r e co mm e n de d t o k e ep t h e t r ace le n g t h les s t h a n 1 i n ch t o 2 in ch es and t o k e ep dif f er en t i al o u t p ut t r ace le n g th s a s eq ual a s pos s i b le . set r i cmos mo de i n a p plic a t io n s t h a t c a n t o lera t e a slig h t deg r a d a t io n i n d y n a mic p e r f o r ma n c e , the ad9444 o u t p u t dr i v ers can b e co nf igur ed t o in t e r f ace wi th 2. 5 v o r 3.3 v logic fa milies b y ma t c hin g d r vdd t o t h e dig i t a l s u p p ly o f t h e in t e r f ace d log i c. cmos o u t p u t s a r e a v a i la b l e w h en o u tp ut mo d e is cmos log i c lo w (o r a g nd fo r co n v enie n c e ) . i n t h is mo de , t h e o u t p ut da t a b i ts a r e sin g le - en de d cmos, d x , as is t h e o v er ra n g e o u t p ut, o r . the o u t p u t clo c k is p r o v ide d as a dif f er en t i al cmos sig n al, d c o+/ d c o ?. l o w e r su p p ly vol t a g es a r e r e commende d to a v o i d co u p ling s w i t c h i n g tra n s i e n t s ba ck t o t h e se n s i t i v e a n alog secti o n s o f th e ad c. th e ca p a ci t i v e lo ad t o t h e cmos o u t p u t s s h o u ld b e mini mi ze d , an d e a ch o u t p u t sho u ld b e con n e c te d to a si n g le g a te t h rou g h a s e r i e s re s i stor ( 2 2 0 ? ) to m i n i m i z e s w itch i n g t r a n sien ts ca us e d b y t h e ca p a c i t i v e lo ading. timi ng the ad9444 p r o v ides l a t c h e d da ta ou t p u t s wi t h a p i p e lin e dela y o f 12 clo c k c y cles. d a t a ou t p u t s a r e a v a i la b l e one p r o p a g a t ion del a y ( t pd ) a f t e r th e ri s i n g ed g e o f c l k + . r e f e r t o f i g u r e 2 a n d f i g u r e 3 f o r d e ta iled tim i n g d i a g ra m s . operational mode se lection dat a for m at select the da t a fo r m a t s e le c t ( d f s ) p i n o f t h e ad944 4 deter m i n es th e co d i n g f o rma t o f th e o u t p u t da ta . t h i s p i n i s 3. 3 v c m o s co m p a t i b le , wi t h log i c hig h (o r a v d d 1, 3.3 v) s e lec t in g tw os co m p lem e n t , and d f s log i c lo w (a gnd) s e lec t in g o f fs et b i na r y f o rm a t . t a b l e 1 0 s u m m a riz e s th e o u t p u t c o d i n g . out p ut mode select the o u p u t m o d e p i n co n t r o ls th e log i c co m p a t ib ili t y , as w e l l as t h e p i n o u t o f t h e dig i tal o u t p u t s. this p i n is a cm os co m p a t i b le i n p u t . w i th o u t p ut m o d e = 0 (a g n d ) , th e ad9444 o u t p u t s a r e cm os-com p a t i b l e and t h e p i n as sig n m e n t fo r t h e de vic e is def i n e d i n t a b l e 8. w i t h ou tp u t mode = 1 (a vd d1, 3.3 v), th e ad9444 o u t p u t s a r e l v ds-co m p a t i b l e an d t h e pin a s sig n men t fo r t h e de vi ce is def i n e d in t a b l e 7. duty cycl e st abilizer the d c s c i r c ui t is co n t r o l l e d b y t h e d c s mod e p i n; a cmo s log i c l o w (a gnd) o n d c s m o d e ena b les the d c s, an d log i c hig h (a vdd1, 3.3 v) dis a b l es t h e con t r o l l er .
ad9444 rev. 0 | page 24 of 40 table 10. digital output coding code vin+ ? vin? input span = 2 v p-p (v) vin+ ? vin? input span = 1 v p-p (v) digital output offset binary (d9??????d0) digital output twos complement (d9??????d0) 16383 1.000 0.500 11 1111 1111 1111 01 1111 1111 1111 8192 0 0 10 0000 0000 0000 00 0000 0000 0000 8191 ?0.000122 ?0.000061 01 1111 1111 1111 11 1111 1111 1111 0 ?1.00 ?0.5000 00 0000 0000 0000 10 0000 0000 0000 evaluation board evaluation boards are offered to configure the ad9444 in either cmos or lvds mode. each represents a recommended configuration for using the device over a wide range of sample rates and analog input frequencies. these evaluation boards provide all the support circuitry required to operate the adc in its various modes and configurations. complete schematics and layout plots follow and demonstrate the proper routing and grounding techniques that should be applied at the system level. it is critical that signal sources with very low phase noise (< 1 ps rms jitter) be used to realize the ultimate performance of the converter. proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. the evaluation boards are shipped with an ac to 6 v dc power supply. the evaluation boards include low dropout regulators to generate the various dc supplies required by the ad9444 and its support circuitry. separate power supplies are provided to iso- late the dut from the support circuitry. each input configura- tion can be selected by proper connection of various jumpers (see figure 47 to figure 50 and figure 59 to figure 61). both the lvds and cmos versions of the evaluation board are compatible with the high speed adc fifo evaluation kit (part number hsc-adc-evala-sc). the kit includes a high speed data capture board that provides a hardware solution for captur- ing up to 32ksamples of high speed adc output data in a fifo memory chip (user upgradeable to 256k samples). software is provided to enable the user to download the captured data to a pc via the usb port. this software also includes a behavioral model of the ad9444 and many other high speed adcs. behavioral modeling of the ad9444 is also available at www.analog.com/adisimadc . the adisimadc? software supports virtual adc evaluation using adi proprietary behavioral modeling technology. this allows rapid comparison between the ad9444 and other high speed adcs, with or without hardware evaluation boards. the ad9444 lvds evaluation board includes an on-board, lvds-to-cmos translator, but the user may choose to remove the translator and terminations to access the lvds outputs directly. the cmos evaluation board includes a buffer for the output data and the dco output clock of the ad9444.
ad9444 rev. 0 | page 25 of 40 lvds evaluation board schem a tics c40 0.1 f 100 ? optional 15 20 23 97 96 86 12 21 22 16 95 24 25 26 27 34 92 93 94 28 29 30 31 40 39 19 41 42 35 38 90 91 87 18 9 64 63 43 44 72 73 76 77 78 79 80 81 45 46 49 50 51 52 55 56 57 58 59 60 65 66 68 69 70 71 6 88 84 85 48 53 61 67 74 82 47 54 62 75 83 32 33 100 89 36 37 101 98 7 14 13 10 99 11 17 2 3 4 5 8 1 vc c gn d r9 1k ? r1 2 r1 5 vc c gn d r3 3.8k ? 5 4 3 2 6 7 8 p5 drbn drn e24 ext r e f d2_cn d2_tn d 3_c n d 3_t n d 4_c n d 4_t n d 5_c n d 5_t n d 6_c n d 6_t n d 7_c n d 7_t /d 0_yn d 8_c /d 1_yn d 8_t /d 2_yn d 9_c /d 3_yn d 9_t /d 4_yn d 10_c /d 5_yn d 10_t /d 6_yn gn d c3 9 10 f gn d dor_t/dor_yn e41 e25 e27 e26 vc c gn d e38 e40 h4 mthole6 e39 gnd gn d c3 0.1 f c9 0.1 f c8 6 0.1 f r1 3.8k ? gn d encb enc drvdd drv dd drv dd drv dd drvdd gnd gn d gn d gn d gn d gnd dor_c/d13_yn d1_tn d1_cn d13_t/d12_yn d13_c/d11_yn d12_t/d10_yn d12_c/d9_yn d11_t/d8_yn d11_c/d7_yn d0_tn d0_cn vc c vc c vc c vcc vcc vcc vcc 5v 5v 5v vcc vcc vcc vc c vc c vcc vc c vc c gn d gnd gnd gn d gn d gn d c1 3 20p f 33 ? r35 r28 33 ? r1 3 xx c91 0.1 f gn d e20 ext r e f gnd vdl gnd drvdd gnd vcc 5v gnd gn d vc c gn d gnd gnd epad ad9444 u1 p i n de fi ni ti o n s lv ds / c m o s r4 36 ? 1 h3 mthole6 h1 mthole6 h2 mthole6 av dd1 dnc dnc dnc o u tp ut m o de dfs lv ds bi as / dnc av dd1 av dd1 sen se vr ef ag nd re ft re fb ag nd av dd1 av dd1 av dd1 av dd2 ag nd vin + vin? ag nd av dd1 av dd1 vcc vcc vcc vcc vcc vcc vcc gnd gnd 1k ? 1k ? gn d r1 4 1k ? e1 e2 e3 gn d vc c c1 2 0.1 f c5 0.1 f j4 gn d r5 xx gn d t5 a d t 1- 1wt 1 5 3 6 2 4 nc ti nb gn d analo g l1 e15 r6 36 ? r2 3.8k ? c51 10 f c2 0.1 f c24 0.1 f gn d gnd 05089-050 a d t 1- 1wt pr i sec nc en c e ncb r39 xx gn d gn d j5 50 ? r7 c26 0.1 f c36 0.1 f xt a l in pu t 1 2 3 5 6 t3 1 3 2 cr2 c4 2 0.1 f gn d 50 ? r8 xtalinputb gn d 4 gn d j1 drv dd drg nd d 10+ d 10? d9 + d9 ? d8 + d8 ? drg nd d7 + d7 ? dco + dco ? drv dd drg nd d6 + d6 ? d5 + d5 ? d4 + d4 ? drv dd drg nd d3 + d3 ? d13? d12+ d12? d11+ d11? dcs mod agnd avdd1 agnd agnd avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 agnd avdd1 agnd or+ or? drvdd drgnd d13+ (msb) avdd1 avdd1 avdd2 avdd2 avdd2 avdd2 agnd c1 avdd1 avdd1 clk+ clk ? avdd1 avdd2 avdd2 avdd1 avdd1 (lsb) d0? d0+ d1? d1+ drvdd drgnd d2? d2+ ou t vc c vee ~ o u t ou tpu t ou tpu t b vc c gn d nc e/d jn 00158 + f o r vec t r on xt a l f o r vf xt a l gn d xt a l in pu t b xt a l in pu t e52 c9 2 0.1 f c4 4 10 f e47 r3 8 xx r27 xx r37 xx r20 xx r1 7 xx r1 9 xx r1 8 xx 4 5 6 3 2 1 u2 8 14 7 u6 ec l o sc r36 xx r4 0 xx c9 3 0.1 f e46 vxt a l gn d gn d gn d xt a l ou t b xt a l ou t xt a l ou t xt a l ou t b 5v vc c gn d gn d gn d vxt a l vxt a l vxt a l vxt a l vxt a l 1 e nco de gn d + gn d tout toutb optional encode circuits encode f i g u re 47. l v ds m o de ev aluat i on b o ard s c h e m a t i c
ad9444 rev. 0 | page 26 of 40 in out out1 3.3v c1 10 f c57 10 f 3 4 2 1 adp3338 u4 gnd gnd vd l vd l gnd vin gnd + + in out out1 3.3v c34 10 f c88 10 f 3 4 2 1 adp3338 u3 gnd gnd drv dd drv dd gnd vin gnd + + in out out1 3.3v c6 10 f c87 10 f 3 4 2 1 adp3338 u15 gnd gnd vc c vc c gnd vin gnd + + in out out1 5v c4 10 f c89 10 f 3 4 2 1 adp3338 u14 gnd gnd 5v 5v gnd vin gnd + + pj-102a c33 10 f 1 3 2 p4 gnd gnd vin + 1 3 2 05089-051 power options f i g u re 48. l v ds m o de ev aluat i on b o ard s c h e m a t i c (co n t i nued) 05089-052 + c64 10 f c75 0.1 f vcc gnd + c65 10 f c47 0.1 f c23 0.1 f c22 0.1 f c21 0.1 f c20 0.1 f drvdd gnd extref gnd + c46 0.1 f c61 0.1 f c60 0.1 f c50 0.1 f c48 0.1 f c27 0.1 f c28 0.1 f c30 0.1 f c32 0.1 f c35 0.1 f c43 0.1 f c90 xx vcc gnd c18 xx c19 xx c29 xx c38 xx c37 xx c31 xx c15 xx c16 xx c17 xx c14 xx c11 xx c10 xx c69 xx c70 xx c45 xx c49 xx c59 xx drvdd gnd + c56 10 f c85 0.1 f c53 0.1 f c52 0.1 f c58 0.1 f 5v gnd c71 xx c72 xx c73 xx c62 xx 5v gnd c55 10 f p19 gnd f i g u re 49. l v ds m o de ev aluat i on b o ard s c h e m a t i c (co n t i nued)
ad9444 rev. 0 | page 27 of 40 p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p29 p31 p33 p35 p37 p39 p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p30 p32 p34 p36 p38 p40 p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p29 p31 p33 p35 p37 p39 p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p30 p32 p34 p36 p38 p40 p3 c40ms gnd pwr 74vcx86 + rso16iso 220 r8 r7 r6 r5 r4 r3 r1 r2 rso16iso 220 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz4 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz5 7 14 11 8 6 3 u10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 p6 c40ms d13o d11o d9o d7o d6o d5o d2o d1o d0o d3o d4o d8o d10o d12o oro d11_c/d7_yn d10_c/d5_yn d9_c/d3_yn d8_c/d1_yn d7_cn drbn d6_cn d5_cn d0_cn d0_tn d1_tn d2_tn d3_tn d4_tn d5_tn d6_tn drn d7_t/d0_yn d8_t/d2_yn d9_t/d4_yn d10_t/d6_yn d11_t/d8_yn d12_t/d10_yn d13_t/d12_yn dro d0o d1o d3o d4o d5o d6o d2o dor_c/d13_yn dor_t/dor_yn d13_c/d11_yn d12_c/d9_yn d1_cn d2_cn d3_cn d4_cn gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd d7o d8o d9o d10o d11o d12o d13o oro e34 e43 e32 vdl gnd gnd5 vcc6 vcc5 gnd4 end d4y d3y d2y d1y enc c4y c3y c2y c1y gnd3 vcc4 vcc3 gnd2 b4y b3y b2y b1y enb a4y a3y a2y a1y ena gnd1 vcc2 vcc1 gnd d4b d4a d3b d3a d2b d2a d1b d1a c4b c4a c3b c3a c2b c2a c1b c1a b4b b4a b3b b3a b2b b2a b1b b1a a4b a4a a3b a3a a2b a2a a1b a1a 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 u7 sn75lvds386 dor_c/d13_yn d13_c/d11_yn d12_c/d9_yn d11_c/d7_yn d10_c/d5_yn d9_c/d3_yn d8_c/d1_yn d3_cn dor_t/dor_yn d13_t/d12_yn d12_t/d10_yn d11_t/d8_yn d10_t/d6_yn d9_t/d4_yn d8_t/d2_yn d7_t/d0_yn d7_cn drn drbn d6_tn d6_cn d5_cn d5_tn d4_tn d4_cn d3_tn d2_tn d2_cn d1_tn d1_cn d0_tn d0_cn drp vdl vdl gnd gnd gnd vdl vdl gnd vdl vdl gnd vdl vdl vdl vdl gnd r8 r7 r6 r5 r4 r3 r1 r2 4y 3y 2y 1y 1 2 4 5 9 10 12 13 1a 1b 2a 2b 3a 3b 4a 4b c76 10 f c97 0.1 f c82 0.1 f c80 0.1 f 81 0.1 f vdl gnd gnd 00 r53 xorn gnd 00 r52 gnd vdl dro 05089-053 f i g u re 50. l v ds m o de ev aluat i on b o ard s c h e m a t i c (co n t i nued)
ad9444 rev. 0 | page 28 of 40 05089-057 f i g u re 51. l v ds m o de ev aluat i on b o ard layout , pri m ar y s i de 05089-058 f i g u re 52. l v ds m o de ev aluat i on b o ard layout , s econd ar y side 05089-059 f i g u re 53. l v ds m o de ev aluat i on b o ard layout , g r ound plan e 1 05089-060 f i g u re 54. l v ds m o de ev aluat i on b o ard layout , g r ound plan e 2 05089-061 f i g u re 55. l v ds m o de ev aluat i on b o ard layout , p o wer pl ane 1 05089-062 f i g u re 56. l v ds m o de ev aluat i on b o ard layout , p o wer pl ane 2
ad9444 rev. 0 | page 29 of 40 05089-063 f i g u re 57. l v ds m o de ev aluat i on b o ard layout , pri m ar y s ilk s c r e e n 05089-064 f i g u re 58. l v ds m o de ev aluat i on b o ard layout , s econd ar y silk s c r e en
ad9444 rev. 0 | page 30 of 40 lvds mode evaluation board bill of materials (bom) table 11. item qty. refdes description manufacturer mfg_part_no 1 1 ad9444pcb pcb, ad9444 lvds engineering evaluation board pcsm ad9444lvdscustrevc 2 16 c1, c4, c6, c33, c34, c39, c44, c55 to c57, c64, c65, c76, c87 to c89 capacitors, tantalum, smt bcaptajc, 10 f, 16 v, 10% kemet t491c106k016as 3 38 c2, c3, c5, c9, c12, c20 to c24, c26 to c28, c30, c32, c35, c40, c42, c43, c46 to c48, c50, c52, c53, c58, c60, c61, c75, c80 to c82, c85, c86, c91 to c93, c97 capacitors, 0.1 f 10 v ceramic x5r 0402 panasonic ecj-0eb1a104k 4 1 c51 capacitor, ceramic 10 f 6.3 v x5r 0805 kemet c0805c106k9pactu 5 1 cr2 diode, dual schottky hsms2812, sot-23, 30 v, 20 ma panasonic ma716-(tx) 6 17 e1 to e3, e24, to e27, e32, e34, e38, e39, e40, e41, e43, e46, e47, e52 40-pin breakable header 3m 2340-611tn 7 2 j1, j4 connector, gold, male, coaxial, sma, vertical johnston comp. 142-0701-201 8 1 l1 10 nh inductor coilcraft 0603cj-10nxgbu 9 1 p3 header, 40-pin, male, 40-pin right angle samtec tsw-120-08-t-d-ra 10 1 p4 power jack swithcraft rapc722 11 1 r3 resistor, 3.6 k? 1/16 w 1% 0402 smd panasonic erj-2gej362x 12 2 r4, r6 resistor, 36 ? 1/16 w 5% 0402 smd panasonic erj-2gej360x 13 1 r8 resistor, 49.9 ? 1/16 w 1% 0402 smd panasonic erj-2rkf49r9x 14 4 r9, r12, r14, r15 resistor, 1.00 k? 1/16 w 1% 0402 smd panasonic erj-2rkf1001x 15 2 r28, r35 resistor, 33 ? 1/16 w 5% 0402 smd panasonic erj-2gej330x 16 3 r39, r52, r53 resistor, 0 ? 1/16 w 5% 0402 smd panasonic erj-2ge0r00x 17 2 rz4, rz5 22 ? resistor array, 16 term cts corp. 742163220jtr 18 2 t3, t5 transformer, adt1-1wt, cd542, adt1-1wt mini-circuits adt1-1wt 19 1 u1 14-bit, 80 msps adc adi ad9444bsvz-80 20 3 u3, u4, u15 3.3 v voltage regulator adi adp3338-3.3 v 21 1 u14 5 v voltage regulator adi adp3338-5.0 v 22 1 u6 clock oscillator, 80 mhz cts reeves mx045-80 23 1 u7 lvds-to-cmos translator with 100 term texas instruments sn75lvdt386dgg 24 1 u10 2 input xor gate fairchild 74vcx86m 25 4 u6 pin sockets, closed end amp 5-330808-3
ad9444 rev. 0 | page 31 of 40 item qty. refdes description manufacturer mfg_part_no 26 24 c10, c11, c13, to c19, c29, c31, c36 to c38, c45, c49, c59, c62, c69, c70 to c73, c90 1 capacitors, select 10 v ceramic x5r 0402 panasonic 27 1 j5 1 connector, gold, male, coaxial, sm a, vertical johnston comp. 142-0701-201 28 2 p5, p6 1 power connectors weiland 29 1 r1, r2, r5, r7, r13 1 resistors, select 1/16 w 1% 0402 smd panasonic 30 1 r17 to r20, r27, r36 to r38, r40 1 resistors, select 1/16 w 1% 0402 smd panasonic 31 5 u2 1 xo select vectron 1 parts not placed.
ad9444 rev. 0 | page 32 of 40 cmos eval uation board schem a tics c40 0.1 f 100 ? optional 15 20 23 97 96 86 12 21 22 16 95 24 25 26 27 34 92 93 94 28 29 30 31 40 39 19 41 42 35 38 90 91 87 18 9 64 63 43 44 72 73 76 77 78 79 80 81 45 46 49 50 51 52 55 56 57 58 59 60 65 66 68 69 70 71 6 88 84 85 48 53 61 67 74 82 47 54 62 75 83 32 33 100 89 36 37 101 98 7 14 13 10 99 11 17 2 3 4 5 8 1 vc c gn d r1 2 1k ? r9 1k ? r2 1 vc c gn d r3 3.8k ? co utb co ut e24 ext r e f d7 t/ d0 y d8 c/ d1 y d8 t/ d2 y d9 c/ d3 y d9 t/ d4 y d 10c /d 5yn d 10t /d 6yn gn d c3 9 10 f gn d dort/dory e41 e25 e27 e26 vc c e38 e40 h4 mthole6 e39 gnd gn d c3 0.1 f c9 0.1 f r1 3.8k ? gn d encb enc drvdd drv dd drv dd drvdd gnd gn d gn d gn d gn d gnd dorc/d13y d13t/d12yn d13c/d11yn d12t/d10yn d12c/d9yn d11t/d8yn d11c/d7yn vc c vc c vc c vcc vcc vcc vcc 5v 5v 5v vcc vcc vcc vc c vc c vcc vc c vc c gn d gnd gnd gn d gn d gn d c1 3 20p f 33 ? r35 r28 33 ? r1 3 xx c91 0.1 f gn d e20 ext r e f gn d vc c gn d gnd gnd epad ad9444 u1 p i n de fi ni ti o n s lv ds / c m o s r4 36 ? h3 mthole6 h1 mthole6 h2 mthole6 vcc vcc vcc vcc vcc vcc vcc gnd gnd 1k ? gn d r1 5 1k ? e1 e2 e3 gn d vc c c1 2 0.1 f c5 0.1 f j4 gn d r5 xx gn d t5 a d t 1- 1wt 1 5 3 6 2 4 nc ti nb gn d analo g l 110n h e15 r6 36 ? r2 3.8k ? c51 10 f c78 0.1 f c2 0.1 f gn d gnd 05089-054 drv dd ct e x t e rnal re fe re nce in pu t a d t 1- 1wt pr i sec nc en c e ncb r39 xx gn d gn d j5 50 ? r7 c26 0.1 f c36 0.1 f xt a l in pu t 1 2 3 5 6 t3 1 3 2 cr2 c4 2 0.1 f gn d 50 ? r8 xt a l in pu t b gn d 4 gn d j1 ou t vc c vee ~ o u t ou tpu t ou tpu t b vc c gn d nc e/d jn 00158 + f o r vec t r on xt a l f o r vf xt a l gn d xt a l in pu t b xt a l in pu t e52 c9 2 0.1 f c4 4 10 f e47 r3 8 xx r27 xx r37 xx r20 xx r1 7 xx r1 9 xx r1 8 xx 4 5 6 3 2 1 u2 8 14 7 u6 ec l o sc r36 xx r4 0 xx c9 3 0.1 f e46 vxt a l gn d gn d gn d xt a l ou t b xt a l ou t xt a l ou t xt a l ou t b 5v vc c gn d gn d gn d vxt a l vxt a l vxt a l vxt a l vxt a l 1 drv dd drg nd d6 d5 d4 d3 d2 d1 drg nd d0 (ls b ) dnc dco + dco ? drv dd drg nd dnc dnc dnc dnc dnc dnc drv dd drg nd dnc dnc avdd1 avdd1 avdd2 avdd2 avdd2 avdd2 agnd c1 avdd1 avdd1 clk+ clk ? avdd1 avdd2 avdd2 avdd1 avdd1 dnc dnc dnc dnc drvdd drgnd dnc dnc av dd1 dnc dnc dnc o u tp ut m o de dfs lv ds bi as av dd1 av dd1 sen se vr ef ag nd re ft re fb ag nd av dd1 av dd1 av dd1 av dd2 ag nd vin + vin? ag nd av dd1 av dd1 c9 6 0.1 f 5 4 3 2 6 7 8 p5 gnd vdl gnd drvdd gnd vcc 5v gnd 1 + gn d tout toutb pr i sec optional encode circuits encode gn d dcs mode agnd avdd1 agnd agnd avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 avdd1 agnd drvdd agnd or (msb) d13 drvdd drgnd d12 d11 d10 d9 d8 d7 f i g u re 59. c m os m o de ev al uat i on b o ar d s c he mat i c
ad9444 rev. 0 | page 33 of 40 in out out1 3.3v c1 10 f c5 7 10 f 3 4 2 1 adp3338 u8 gnd gnd vd l vd l gnd vin gnd + + in out out1 3.3v c34 10 f c8 8 10 f 3 4 2 1 adp3338 u3 gnd gnd drv dd drv dd gnd vin gnd + + in out out1 3.3v c6 10 f c87 10 f 3 4 2 1 adp3338 u15 gnd gnd vc c vc c gnd vin gnd + + in out out1 5v c4 10 f c89 10 f 3 4 2 1 adp3338 u14 gnd gnd 5v 5v gnd vin gnd + + pj-102a c33 10 f 1 3 2 p4 gnd gnd vin + 1 3 2 05089-055 f i g u re 60. c m os m o de ev al uat i on b o ar d s c he mat i c (co n t i nu ed)
ad9444 rev. 0 | page 34 of 40 p1 p3 p5 p7 p9 p11 p13 p15 p17 p19 p21 p23 p25 p27 p29 p31 p33 p35 p37 p39 p2 p4 p6 p8 p10 p12 p14 p16 p18 p20 p22 p24 p26 p28 p30 p32 p34 p36 p38 p40 p3 c40ms gnd pwr u4 74vcx86 + rso16iso 220 r8 r7 r6 r5 r4 r3 r1 r2 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz4 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz5 7 14 11 8 6 3 u10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 d13m d11m d9m d7m d6m d5m d2m d1m d0m d3m d4m d8m d10m d12m orm drm d0m d1m d3m d4m d5m d6m d2m gnd gnd gnd gnd d7m d8m d9m d10m d11m d12m d13m orm e30 e32 e31 vdl gnd u5 sn74lvch16373a r8 r7 r6 r5 r4 r3 r1 r2 4y 3y 2y 1y 1 2 4 5 9 10 12 13 1a 1b 2a 2b 3a 3b 4a 4b c66 10 f c25 0.1 f c41 0.1 f c24 0.1 f vdl gnd gnd 00 r16 xorzin gate2 00 r42 gnd vdl drm 05089- 056 rso16iso 220 r8 r7 r6 r5 r4 r3 r1 r2 rso16iso 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz4 8 7 6 5 4 3 1 2 16 15 14 13 12 11 10 9 rz1 r8 r7 r6 r5 r4 r3 r1 r2 220 rz2 d7t/d0y d8c/d1y d8t/d2y d9c/d3y d9t/d4y d10c/d5y d10t/d6y d11c/d7y d11t/d8y d12c/d9y d12t/d10y d13c/d11y d13t/d12y dorc/d13y dort/dory xor2in 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 45 39 34 28 48 25 42 31 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 4 10 15 21 7 18 1 24 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1q1 1q2 1q3 1q4 1q5 1q6 1q7 1q8 2d1 2d2 2d3 2d4 2d5 2d6 2d7 2d8 2q1 2q2 2q3 2q4 2q5 2q6 2q7 2q8 gnd le1 le2 vcc oe1 oe2 vcc vcc vcc gnd gnd gnd gnd gnd gnd gnd q = output d = input gnd vdl gnd gnd gnd xor2in vdl gnd gnd vdl gnd gnd vdl gnd gnd rso16iso 220 rz5 00 r14 drm 00 r41 gate c68 0.1 f c67 0.1 f 63 0.01 f e45 e49 e42 vdl gnd 00 r50 not placed coutb cout f i g u re 61. c m os m o de ev al uat i on b o ar d s c he mat i c (co n t i nu ed)
ad9444 rev. 0 | page 35 of 40 05089-065 f i g u re 62. c m os m o de ev al uat i on b o ar d l a yout , p r im ar y side 05089-066 f i g u re 63. c m os m o de ev al uat i on b o ar d l a yout , s e c o nd ar y sid e 05089-067 f i g u re 64. c m os m o de ev al uat i on b o ar d l a yout , groun d pla n e 1 05089-068 f i g u re 65. c m os m o de ev al uat i on b o ar d l a yout , groun d pla n e 2 05089-069 f i g u re 66. c m os m o de ev al uat i on b o ar d l a yout , p o wer p l an e 1 05089-070 f i g u re 67. c m os m o de ev al uat i on b o ar d l a yout , p o wer p l an e 2
ad9444 rev. 0 | page 36 of 40 05089-071 f i g u re 68. c m os m o de ev al uat i on b o ar d l a yout , p r im ar y silk s c r e en 05089-072 f i g u re 69. c m os m o de ev al uat i on b o ar d l a yout , s e c o nd ar y si lk s c reen
ad9444 rev. 0 | page 37 of 40 cmos mode evaluation board bill of materials (bom) table 12. item qty. refdes description manufacturer mfg_part_no 1 1 ad9444pcb pcb, ad9444 lvds evalua tion board pcsm ad9444lvdscustrevc 2 16 c1, c4, c6, c33, c34, c39, c44, c55 to c57, c64 to c66, c87 to c89 capacitors, tantalum, smt bcaptajc, 10 f, 16 v, 10% kemet t491c106k016as 3 32 c2, c3, c5, c9, c12, c20 to c23, c26 to c28, c30, c32, c35, c40, c42, c43, c46 to c48, c50, c52, c53, c58, c60, c61, c75, c78, c85, c91, c92 capacitors, 0.1 f 10 v ceramic x5r 0402 panasonic ecj-0eb1a104k 4 5 c24, c25, c41, c67, c68 capacitors, 0.1 f 16 v ceramic x7r 0603 panasonic ecj-1vb1c104k 5 1 c51 capacitor, ceramic 10 f 6.3 v x5r 0805 kemet c0805c106k9pactu 6 1 cr2 diode, dual schottky hsms2812, sot-23, 30 v, 20 ma panasonic ma716-(tx) 7 20 e1 to e3, e24 to e27, e30 to e32, e38 to e42, e45 to e47, e49, e52 40-pin breakable header 3m 2340-611tn 8 2 j1, j4 connector, gold, male, coaxial, sma, vertical johnston comp. 142-0701-201 9 1 l1 10 nh o402 inductor coilcraft 0402cs-10nx_b_ 10 1 p3 header, 40-pin, male, 40-pin right angle samtec tsw-120-08-t-d-ra 11 1 p4 power jack swithcraft rapc722 12 1 r3 resistor, 3.6 k? 1/16 w 1% 0402 smd panasonic erj-2gej362x 13 2 r4, r6 resistors, 36 ? 1/16 w 5% 0402 smd panasonic erj-2gej360x 14 1 r8 resistor, 49.9 ? 1/16 w 1% 0402 smd panasonic erj-2rkf49r9x 15 4 r9, r12, r15, r21 resistors, 1.00 k? 1/16 w 1% 0402 smd panasonic erj-2rkf1001x 16 2 r14, r50 resistors, 0 ? 1/10 w 5% 0603 smd panasonic erj-3gey0r00v 17 2 r28, r35 resistors, 33 ? 1/16 w 5% 0402 smd panasonic erj-2gej330x 18 1 r39 resistor, 0 ? 1/16 w 5% 0402 smd panasonic erj-2ge0r00x 19 4 rz1 to rz3, rz6 220 ? resistor array, 16 term cts corp. 742163221jtr 20 2 t3, t5 transformer, adt1-1wt, cd542, adt1-1wt mini-circuits adt1-1wt 21 1 u1 14-bit, 80 msps adc adi ad9444bsvz-80 22 4 u3, u8, u15 3.3 v voltage regulator adi adp3338-3.3 v 23 1 u14 5 v voltage regulator adi adp3338-5.0 v 24 1 u5 16-bit flip flop fairchild 74lvth162374 25 4 u6 pin sockets, closed end amp 5-330808-3
ad9444 rev. 0 | page 38 of 40 item qty. refdes description manufacturer mfg_part_no 26 26 c10, c11, c13, c14 to c19, c29, c31, c36 to c37, c38, c45, c49, c59, c62,c69, c70 to c73, c90, c93, c96 1 capacitors, select 10 v ceramic x5r 0402 panasonic 27 1 j5 1 connector, gold, male, coaxial, sm a, vertical johnston comp. 142-0701-201 28 15 r1,r2,r5,r7, r13, r17 to r20, r27, r36 to r40 1 resistors, select 1/16 w 1% 0402 smd panasonic 29 3 r16, r41, r42 1 resistors, select 1/16 w 5% 0603 smd panasonic 30 1 c63 1 capacitor, select 10 v ceramic x5r 0603 panasonic 31 1 u4 1 xor 74vcx86d fairchild 74vcx86d 32 2 p5, p6 1 power connectors weiland 1 parts not placed.
ad9444 rev. 0 | page 39 of 40 outline dimensions compliant to jedec standards ms-026aed-hd notes 1. center figures are typical unless otherwise noted. 2 . the package has a conductive heat slug to help dissipate heat and ensure reliable operation o f the device over the full industrial temperature range. the slug is exposed on the bottom of the package and electrically connected to chip ground. it is recommended that no pcb signa l traces or vias be located under the package that could come in contact with the conductiv e slug. attaching the slug to a ground plane will reduce the junction temperature of the device which may be beneficial in high temperature environments. 3. the exposed heat sink soldered to the ground plane is required for the 100-lead tqfp/ep. 1 25 26 50 76 100 75 51 14.00 sq 16.00 sq 0.27 0.22 0.17 0.50 bsc 1.05 1.00 0.95 0.15 0.05 0.75 0.60 0.45 seating plane 1.20 max 1 25 26 50 76 100 75 51 6.50 nom 7 3.5 0 coplanarity 0.08 0.20 0.09 top view (pins down) bottom view (pins up) conductive heat sink f i g u re 70. 1 00-l e a d thin q u ad f l at p a ckag e , e x pos e d p a d [ t qfp _e p ] (sv - 10 0-1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package outlin e ad9444bsvz-80 1 C40c to +85c 100-lead tqfp_ ep sv-100-1 ad9444-cmos/pcb cmos mode ev aluation board ad9444-lvds/p cb lvds mode evaluation board 1 z = pb-free part.
ad9444 rev. 0 | page 40 of 40 notes ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d05089C0C 10/04(0)

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